The Cadence Processor CPU Core is used in high performance blocks of complex SoC's. This is one of the best kept secrets within the semi IP ...
The Cadence Processor CPU Core is used in high performance blocks of complex SoC's. This is one of the best kept secrets within the semi IP world powering AR/VR, HiFi Audio and Speech, Vision, Imaging and hundreds of intelligent IoT applications. The Tensilica processor is the next generation embedded core that will meet the demands of the Edge of ML and AI. We are extending the reach of our platform to help companies like Amazon, Facebook, Google, Microsoft and Intel to mention just a few of the companies embedding our core into there products. Come be part of the next explosion of embedded devices building a key part of our processor generating platform for CPU's and DSP's.
Sr. Compiler Design Engineer for Neural Net Glow Compiler
Tensilica IP division of Cadence is looking for a compiler developer to join our world-class compiler team. Our C/C++ compiler features numerous highly advanced optimizations and plays a crucial role in the continued success of Xtensa processors.
- Software design and implementation of back-end optimizations for the Xtensa processor architecture
- Software design and implementation of the LLVM and OpenCL ports for the Xtensa architecture
- Benchmark evaluation for customer engagements and decisions on long-term architectural directions
- M.S. or Ph.D. degree in Computer Science with an emphasis on compilers or a related field. Outstanding candidates with a B.S. degree will be considered.
- 2+ years of research or development experience in the compiler field.
- Strong C/C++ development skills
- Academic or industrial background in compiler optimizations
- Previous experience with LVM or OpenCL
- Good understanding of processor architecture concepts